Increase the efficiency of Network on Chip using buffer sharing mechanism

This paper proposes DAMQSV and DAMQS algorithms for systems on chip applications that require an interconnection network. The proposed schemes are based on a DAMQ buffer hardware design. DAMQSV and DAMQS are excellent schemes to optimize buffer management providing a good throughput when the network has a larger load. They can utilize significantly less buffer space without sacrificing the network performance. Implementing the proposed schemes in hardware requires minor modifications to early implementations of the self-compacting buffer. DAMQS provides an excellent approach to optimize buffer management providing a good throughput when the network has a larger load. DAMQSV scheme lets virtual channels from different physical channel share free buffer space. We have discussed simulation results by comparing with SAMQ and DAMQ algorithms. Extensive simulations were performed on ModelSim to evaluate the performance of these buffer schemes. The simulations results on different network configurations, such as different traffic mode, network size, virtual channel number, buffer size per virtual/physical channel and routing protocols, were presented to show that these novel buffer schemes especially the DAMQSV scheme are efficient buffer organization methods to be used in the network on chip.